Inter Connects - What I know and don't know

Also want to add that the OCC I believe is the Ohno continuous casting. This was a major advance by Japanese researcher Ohno with continuous casting in one crystal. Thus, there are not variable size crystal grains and grain boundaries to deal with for the electrical current. Also reducing the level of non-conducting elements like oxygen has been a major improvement. Annealing heat treatments likely reduces stresses (though heat treatments can impact overall composition if look at material diagrams). Perhaps that is what happens with the mysterious burn in. Some talk about moving cables even producing temporary stresses which may impact sound. I have found that raising cables off the carpeting does impact the sound, likely due to static electricity of the carpeting impacting the charged dielectric. 

Maybe I was being presumptuous by assuming that the signals pins == "signal circuitry" in the diagram.

@nquery You were. the lines from the bottom of the 'signal circuitry' box are ground connections. The signal passes from left to right in the diagram.

This document relates to how EMI circuitry should be used in balanced connections to deal with high frequency issues that may result in noise. So it shows a variety of hookups and shows how a number of them can be problematic.

In any even while the signal circuit does use ground as a reference, the signal current does not enter or use ground. For example in our preamps, which have a patented direct-coupled balanced tube output, if you ground one side or not, the signal level remains constant; IOW is the same amplitude.

I'd be very interested to see a circuit where signal currents are not present in the ground, yet when operated balanced you get double the output you do single-ended!

@atmasphere ok, one last thing then and i’ll stop harassing you :) .... where in the AES48 doc does it define the requirement for the signal current (pin 2 and pin 3) to reference each other and not reference the ground in order to be compliant? because other than that, on the face of it it would seem that T+A is meeting the requirements as laid out in this doc. (and the recommended practice in the other Rane article you linked).

[edit - to be more succinct, this AES48 doc only discusses shield connectivity and the "pin 1 problem" as per it's introduction. I see no discussion on pin2 and pin3 grounding which I thought you had said was part of AES48 ]

fyi, I have only become interested in this topic after having bought a pair of your fantastic class-D’s and maybe looking at a new DAC sometime soon. Not having to worry about balanced interconnects (as much) would be nice.