Inter Connects - What I know and don't know

@atmasphere

Hi, I asked T+A about whether or not their DAC 200 is AES48 compliant and they responded:

"The AES48 standard was paid attention to when designing this DAC. There is a small difference, though: the connection between pin1 and enclosure is not direct but via a 100nF cap. This cap has no negative effect on EMI or shielding."

However, their specs state 2.5V SE and 5V Balanced i.e. the typical doubling of output for non compliant balanced output. ("High level (RCA) 0...2,5 Veff / 22 Ohms, balanced (XLR) 0...5,0 Veff / 22 Ohms")

What do you make of their statement? As per your post above it sounds like this DAC is NOT AES48 ...

@atmasphere

fyi, here is a portion of a followup response from T+A regarding AES48 compliance. I tried to parse the diagram in the draft AES doc but this is now officially way over my head :)

The analog signal circuitry of the DAC200 is referenced to the analog signal ground. This conforms to AES48 (see "REF" ground in figure_3 of draft AES48-20XX).

The generation of the balanced audio signal is already done in digital domain - not in analog domain. So this balanced signal is not generated relative to any (analog) ground.

[edit - another point of contention is that AES48 is concerned with the connectors, not the cable between them]

@atmasphere  thanks for the followup and link. I read it and understand it in and of itself.

T+A previously stated that pin 1 is connected to the enclosure (chassis) and not signal ground so this would suggest that they do match the "recommended practice" in Figure 1b of the article you linked. i.e. "equipment using 3-pin, XLR-type connectors must tie pin 1 to the chassis (usually called chassis ground) -- not the audio signal ground as is most common."

So far so good. Now, that's where the article you linked stops.

T+A then said "The analog signal circuitry of the DAC200 is referenced to the analog signal ground" and that this matches figure 3 in AES48 Draft. In this figure 3, the pin 2 and pin 3 (signal circuits) are tied to the REF = "Signal Reference" which I assume is what they meant when they said "signal ground".

This is where I am having a disconnect - isn't this the same thing as when you state that pin 2 and pin 3 need to reference each other and not 'ground'?? I assume you mean chassis ground, not the REF = Signal Reference in the AES diagram.

I don't believe the DAC uses an output transformer ('The generation of the balanced audio signal is already done in digital domain - not in analog domain.') so isn't it possible that the differential circuit could legitimately push out twice voltage for balanced vs SE and still remain AES48 compliant?

Thanks for your patience and understanding, I am learning a lot.

@atmasphere See figure 3 on page 7 of AES48 Draft. Maybe I was being presumptuous by assuming that the signals pins == "signal circuitry" in the diagram. The REF label is next to the black lines coming down from "signal circuitry".

@atmasphere ok, one last thing then and i’ll stop harassing you :) .... where in the AES48 doc does it define the requirement for the signal current (pin 2 and pin 3) to reference each other and not reference the ground in order to be compliant? because other than that, on the face of it it would seem that T+A is meeting the requirements as laid out in this doc. (and the recommended practice in the other Rane article you linked).

[edit - to be more succinct, this AES48 doc only discusses shield connectivity and the "pin 1 problem" as per it's introduction. I see no discussion on pin2 and pin3 grounding which I thought you had said was part of AES48 ]

fyi, I have only become interested in this topic after having bought a pair of your fantastic class-D’s and maybe looking at a new DAC sometime soon. Not having to worry about balanced interconnects (as much) would be nice.