Signal in the cable reflects on impedance boundaries, so matching characteristic impedance of the cable to output/input impedance of your gear is important and the cheaper cable might be a better match in your system than expensive one. If your master clock requires 50ohm don't even try 75ohm - it doesn't make sense.
Reflections in the cable happen when cable becomes transmission line. Rule of thumb says that it happens when signal travels longer than 1/8 of transition time. With typical 25ns transitions it would be (assuming 5ns/m) around 0.6m, but I wouldn't risk more than 1 foot, because length of connections inside of the gear (on both sides) counts. Most likely you need longer cable and when you don't have perfect impedance match reflections will happen. The key is for the first reflection (initiated by the beginning of the level change (knee)), to come back after threshold point. We don't want reflection to modify (to add to) transition. Assuming threshold point in the middle it has to come later than typical 25ns divided by 2 = 12.5ns. So signal has to travel both ways longer than 12.5ns equal to 1.25m. For different transition times it will be different. Your gear might swing in 30ns and min cable length will be 1.5m. Transition time is difficult to measure (without affecting it), while speed of electricity in the cable is dielectric dependent. Because of that it comes to trial and error.
Transitions are square in S/Pdif and your master clock. I would expect faster transition times with better transports or perhaps your master clock. Faster transitions reduce noise induced jitter (weakness of Toslink). As for all inputs reclocking S/Pdif signal it is not like that. Most of them have PLL (Phase Lock Loop) that adjust internal D/A conversion clock to average S/Pdif signal rate. Since time constant is involved (averaging) PLLs are not perfect and can even produce small frequency oscillations of D/A clock. Reclocker, like one in my Benchmark, uses asynchronous rate conversion, to produce D/A conversion clock, that doesn't even have to be a multiple of S/Pdif (as it is with PLL). My older reclocking DAC Benchmark DAC1 had D/A conversion at fixed 110kHz independent of incoming S/Pdif signal. Reclocking process inside of Benchmark DACs reduces D/A conversion time jitter. Absence of jitter (that converts to noise in frequency domain) makes signal surprisingly clean.
