Sampling clock jitter is inherent to the digitization process so it can't be removed by anything in the playback chain. Here's a good overview from Texas Instruments on how sampling clock jitter affects ADC performance - https://www.ti.com/lit/an/slyt338/slyt338.pdf?ts=1698696178966&ref_url=https%253A%252F%252Fwww.google.com%252F
Practically speaking, given today's ADC performance, clock accuracy and the relatively low input frequencies of audio vs. sampling a signal at radio frequencies, this type of jitter can most likely be considered inaudible.
For example in the paper linked above, the 'average' jitter is calculated at 26 ps which equates to spurious frequency components that are ~100 dB below the RF carrier frequency. If we translated this to an example at audio frequencies, even with music playing at rock concert levels (110 dB), the jitter would still be quieter than a whisper (~10 dB). If we also account for the fact that we now have sampling clocks with femtosecond accuracy (as in the case of RME's SteadyClock technology), the jitter components will be below the threshold of perception in virtually all cases.