Denafrips Pontus II Clicks Or Static?

@whipsaw - You can call it a hardware problem if you want, but IMO, it was (is) a rational approach to solving the problem of jitter reduction of source-clocked digital data. I'm sorry you experienced problems with your DAC.

With their implementation as I understand it (and I am a digital electronics engineer), there is no "definitive" fix if the source and DAC have significantly different clock frequencies. I suspect this new firmware either increases the amount of RAM allocated to the FIFO, changes the algorithm used to reset the FIFO pointers (e.g. between every song), or both. This won't fix all possible cases, but it will likely reduce the percentage of users that experience the problem from an already small number to near zero.

I don't know why Denafrips chose to wait as long as they did to issue a fix. It could be that other more significant changes were required to the firmware to allocate more RAM for the FIFO, or it could be that they just felt it was affecting so few users that they had other priorities. 

At any rate, hopefully this will fix the problem for the users that FIFO overflow/underflow was affecting. 

I'm quite happy with the sound from my T+, but I'm looking forward to being able to try out this new update. I've never experienced any skipping/glitching issues, but I have always used my T+ with a USB connection to my streamer (through a Gaia). 

@whipsaw - I am making some assumptions here on the exact implementation of Denafrips' designs, since they have never really published a detailed description.

As I understand it, the input data is clocked into the FIFO using the source device's clock (embedded in the SPDIF signal), and clocked out of the FIFO using the DAC's internal clock.

If the clocks are different enough in frequency, eventually the FIFO will overflow (if the source device's clock is faster) or underflow (if the source clock is slower). So, yes, CISCO's explanation is basically correct.

I'm not an expert on modern DAC implementation, but I believe that many DACs (particularly lower priced DACs) use a phase-locked loop to adjust the DAC's clock frequency to match the source clock. They may also use a FIFO so the PLL can be slow responding to minimize jitter. But a PLL will still not be as stable and jitter free as a fixed crystal oscillator (particularly an temperature controlled oscillator).

I suspect the reason that the problem was less common (or non-existent) with the Terminator and T+ is that the clock used in these DACs is higher quality (more accurate) than the clocks used in the lower priced models, and these DACs probably also tend to be used with higher quality sources (which have more accurate clocks). I have not heard that the FIFO implementation is any different, although it's possible that larger FIFOs were used. 

I also suspect that many higher end DACs use a similar approach to Denafrips and just did a better job with the FIFO management (perhaps using the same approach that Denafrips is now using).