@gdhal
The asynchronous clock is an example of jitter rejection. In the case of Benchmark, the incoming clock is digitally separate from the outgoing clock. Adjustments are made digitally at precisely 4 pSec intervals at an adjustment rate of less than 1Hz in order to match timing. If you can’t hear below 1 Hz then there is no audible jitter from the incoming clock reaching the DAC chip. It is quite simple to do this digitally - it is much harder to do things analog as 4 pSec accuracy is extreme.
The asynchronous clock is an example of jitter rejection. In the case of Benchmark, the incoming clock is digitally separate from the outgoing clock. Adjustments are made digitally at precisely 4 pSec intervals at an adjustment rate of less than 1Hz in order to match timing. If you can’t hear below 1 Hz then there is no audible jitter from the incoming clock reaching the DAC chip. It is quite simple to do this digitally - it is much harder to do things analog as 4 pSec accuracy is extreme.