The asynchronous clock is an example of jitter rejection. In the case of Benchmark, the incoming clock is digitally separate from the outgoing clock. Adjustments are made digitally at precisely 4 pSec intervals at an adjustment rate of less than 1Hz in order to match timing. If you can’t hear below 1 Hz then there is no audible jitter from the incoming clock reaching the DAC chip. It is quite simple to do this digitally - it is much harder to do things analog as 4 pSec accuracy is extreme.
This is a good way to reclock because it does not change the data, but it has performance limitations. I had a product previous to the Synchro-Mesh that did something similar, adjusting every few seconds slightly higher and lower in frequency to "bracket" the incoming frequency in order to clock the output of a FIFO. Been there, done that. There are many of these still in use.
The problem is not the technique, it is the quality of the local master clock and associated circuitry and the quality of the power supply powering it and the decoupling caps etc.. If the clock is controllable in any way and not just free-running, it will never have the low jitter that is possible with a free-running clock IME. My own solution like this had this problem, so ultimately I went to the resampler instead.
Steve N.
Empirical Audio
