MW - There are several techniques. Lets address each of them:
Synchronous buffering:
With synchronous buffering, the same clock is moving the data in and out of the FIFO buffer, so the incoming clock jitter matters.
Local PLL clock:
If you have a local clock that is locked to the incoming clock with a PLL to clock the data out of the FIFO, then the PLL filter loop is affected by the jitter.
Bang-Bang bracketing system:
If you have a bang-bang system that clocks the data out of the FIFO using a local clock which moves the frequency slightly up and down to bracket the frequency of the incoming clock, then this has the potential to minimize the effects of incoming jitter. IT is actually not meeting the spec. for sample-rate frequency though. This is one of two techniques that can actually be immune to incoming jitter. The problem is that it takes 12 custom oscillators, all with low jitter to pull this off. If one designs it any other way, then the jitter of the local clock is the problem. There are a couple of DACs out there that do this, but their jitter is not very low.
Resampling system:
A resampler uses separate local clocks to reclock the data at a new frfequency after it is synchronously buffered to achieve a small delay. Resampling is the second technique that in theory has the potential to be totally immune to incoming clock jitter. It maintains the proper sampling frequencies. The reality is that even the best reclockers, including mine are still slightly affected by incoming jitter. This is likely due to the implementation of the resampling chips.
Steve N.
Empirical Audio
