Maybe the paper referenced below will shed some light on the complexity of jitter for those that believe that a simple value in some clock or DAC datasheet can Trump this effect for good.
Audibility of some forms of jitter on DACs and ADCs have been investigated, but I believe that the improvements that most of us hear when jitter is reduced tend to indicate that audibility thresholds are not so easy to define and greatly depend not only on the technology used inside the chips, but also on the implemented circuitry around those chips (e.g. power supply management).
My 2 cts worth, /patrick
https://statics.cirrus.com/pubs/whitePaper/WP_Specifying_Jitter_Performance.pdf
Audibility of some forms of jitter on DACs and ADCs have been investigated, but I believe that the improvements that most of us hear when jitter is reduced tend to indicate that audibility thresholds are not so easy to define and greatly depend not only on the technology used inside the chips, but also on the implemented circuitry around those chips (e.g. power supply management).
My 2 cts worth, /patrick
https://statics.cirrus.com/pubs/whitePaper/WP_Specifying_Jitter_Performance.pdf