DAC Input Topology


I have a Holo May DAC KTE and all digital in is captured by a proprietary PLL (phase lock loop) circuit which uses a crystal Voltage Controlled Oscillator (VCXO) and discrete voltage regulators to eliminate jitter.  They make clear that all inputs are processed the same.  Is this the primary method used by most (all) DACs?  
I ask because I was previously convinced that I wanted to buy a steamer with I2s out.  I was under the impression that a great clock in the streamer would be passed to the DAC, but PLL doesn’t use the streamer’s clock.  My fallback was USB and the May DAC KTE makes claims regarding the quality of their USB interface.  In fact USB is the manufacturers preferred input.   Now I’m looking at the Aurender N20.  The selling point here is the OCXO clock, which is four to ten times more stable than the Holo’s clock.  Many find the AES, or coax to provide the best sound.  Those that prefer AES, does your DAC use the same voltage driven clock PLL design?  How does the Aurenders clock provide superior sound when the sampling clock is an order of magnitude less stable?   I’m trying to decide on if I’m buying a high quality USB, or AES cable.  Maybe both at some point, but budget only allows one at this point.

vonhelmholtz

Showing 2 responses by designsfx

@vonhelmholtz 

taken from your post-

”I was questioning if the Holo can take advantage of this given that the clock quality/stability is very good, but 4-10 times less stable than the Aurender clock”.

How did you come to realize that the clock in the Holo May is 4-10x less stable?
 

@vonhelmholtz-

I’m not a “clocking” expert by any stretch of the imagination so take this for what it’s worth but as the N20 you’ve inquired about isn’t functioning as a master clock (meaning there are not clocking outputs and the Holo has no clocking inputs) then one could only expect the benefit to be seen (if any) within the quality of the signal sent from the Aurender. If this signal were superior in performance (audible or not) then the Holo’s PLL function would see the benefit. My understanding of a PLL circuit is to regulate the incoming data stream via VCO to keep all within spec. Again, I’m not the expert but without a Master clock both devices would only be working within their own capabilities.